nSealr One

Research family for a purpose-built persistent-secret Nostr hardware wallet, now targeting a minimal, all-SMD, display-agnostic board (KiCad custom-wallet-min). The old complex board is archived. A hardened Rust firmware on an ESP32-S3-WROOM-1-N16R8 host signs behind a TROPIC01-backed encrypted vault; the previous over-scoped board is superseded.

Feature Target Current Contract
request_validation_v0 required planned signing-request-v0+implementation-limits-v0+invalid-vectors
nostr_event_review_universal required planned trusted-review-v0+review-detail-pages-v0
review_detail_pages required planned review-detail-pages-v0
approval_digest_binding required planned approval-digest-v0
physical_approval required planned physical-approval-v0
sign_event_bip340 required research nostr-sign-event-bip340-v0
persistent_secret_custody required research persistent-secret-custody-v0
secure_boot_hardening required research firmware-boot-hardening-v0
device_display_review required planned device-display-review-v0
response_verification required planned signed-response-verification-v0
stateless_session_custody forbidden forbidden

Hardware target

  • Host: ESP32-S3-WROOM-1-N16R8.
  • Vault: a mandatory TROPIC01 open secure element — encrypted seed vault, hardware-PIN anti-bruteforce, TRNG/PUF, attestation, Ed25519/P-256.
  • Key-split SE: a provisioned 2nd-vendor secure element — OPTIGA Trust M populated by default, ATECC608B alternate (DNP) — for a Coldcard-style key-split.
  • I/O: USB-C, a physical confirm button, and an external SPI panel driven over an FPC connector (reference Waveshare 1.69-inch ST7789V2/CST816). No JavaCard, no socket, no NFC, no camera.
  • Power: battery-operable — USB-C and an optional MX1.25 LiPo battery (user-supplied) both power the board.
  • Transport: USB-C is the only v1 signing transport (spec §3).
  • Gated ports: a Qwiic/STEMMA-QT I²C port plus a 0.1-inch expansion header, both default-off (no attack surface when unused). The WROOM module’s BLE radio is present but disabled by default and out of scope for v1 (NIP-46-over-BLE reserved as a future opt-in, never enabled in a high-assurance profile); WiFi is never used.

Security model

This board is the hardened firmware-signer + SE-backed vault + key-split model (mainstream Trezor/Coldcard tier), not an in-card signer:

  • The Rust firmware signs secp256k1 ECDSA + BIP-340 Schnorr on the ESP32-S3 host: the seed is unwrapped from the TROPIC01 vault into RAM at sign time and wiped after. All-signatures-in-SE is an explicit non-goal here — the in-card signing gate belongs to nSealr Card only.
  • The seed is stored encrypted in TROPIC01 behind a hardware PIN enforced by TROPIC01 anti-bruteforce (escalating delays; configurable wipe-after-N). The decryption key is split MCU + TROPIC01 + 2nd-vendor SE, so no single chip holds the plaintext.
  • TROPIC01’s own Ed25519/P-256 signing is reserved for SSH/FIDO/attestation, not Nostr Schnorr.
  • Anti-klepto sign-to-contract and RAM wipe post-sign apply. A duress/decoy-wallet PIN is tracked [DEC] for v1.1 (spec §6), not this phase’s gate.

Secret lifecycle

persistent-secret-custody-v0 is a checked lifecycle contract: no plaintext secrets at rest, wrapped/encrypted storage only before persistent custody, ESP32-S3 RAM-only plaintext after TROPIC01-assisted unlock, required wipe events, and disabled-by-default backup/export behind local review plus physical approval. The seed is generated on device (TROPIC01 TRNG) or imported from BIP-39 words; backup-at-creation exports BIP-39 words plus a SeedQR on the trusted display, one-time, at seed creation; an optional BIP-39 passphrase is supported.

Repository

Open hardware: github.com/nSealr/hardware. ESP32 firmware references: github.com/nSealr/esp32.